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| Integrated Circuit Systems, Inc. ICS9159-12 Frequency Generator and Buffers for Mobile Pentium Systems The ICS9159-12 generates all clocks required for mobile microprocessor systems based on Pentium/Mobile Triton chip sets. Three different reference frequency multiplying factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific plications. A test mode is provided to drive all clocks directly. High drive BCLK outputs provide greater than 1V/ns slew rate into 30pF loads. PCLK outputs provide better than 1V/ ns slew rate into 20pF loads while maintaining 5% duty cycle. General Description Features Block Diagram Generates 14 clocks including processor, disk and reference Meets all Pentium/Mobile Triton 82430MX requirments Independent buffers provide 4 and 6 clock copies Buffered clocks skew matched to 250ps Buffer inputs are 5V tolerant Test clock mode eases system design Selectable multiplying and processor/bus ratios Custom configurations available 3.0V- 5.5V supply range 28pin, .209" SSOP package Pin Configuration Functionality FS1 0 0 1 1 FS0 0 1 0 1 *VCO 118/17*X1 65/7*X1 92/11*X1 Test mode X1, REF (MHz) 14.318 14.318 14.318 TCLK CPU (MHz) 50 (49.69) 66.6 (66.47) 60 (59.87) TCLK/2 28-Pin SSOP *VCO range is limited form 60 - 200 MHz. CPU VCO/2 TCLK/2 9159-12 Rev B 071797 24M 24 MHz TCLK/4 Pentium is a trademark of Intel Corporation. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9159-12 Pin Descriptions PIN NUMBER 8, 25 1 2 3 4 5 11, 23 6, 7, 9, 10 13, 12 14, 20 15, 16, 18 19, 21, 22 24 26 28, 27 PIN NAME VDD X1 X2 OEN BPIN BHIN GND BH(0:3) FS(0:1) VDD BP(0:5) CPU 24M REF(0:1) TYPE PWR IN OUT IN IN IN PWR OUT IN PWR OUT OUT OUT OUT DESCRIPTION Power for logic, CPU and fixed frequency output buffers. XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 10 - 30 MHz XTAL. XTAL output which includes XTAL load capacitance. OEN tristates all outputs when low. This input has an internal pull-up device. Input to BPIN(0:5) buffers. Input to BHIN(0:3) buffers. Ground for logic, CPU and fixed frequency output buffers. Buffered copies of the BHIN input, typically used to drive the PCI device clock inputs at one half the CPU frequency. Frequency multiplier select pins. See table below. These inputs have internal pull-up devices. Power for BCLK output buffers. Buffered copies of the BPIN input, typically used to drive the host device clock inputs at the CPU frequency. 17 VSS PWR Ground for BCLK output buffers. The CPU output, which is a multiple of the input reference frequency as shown in the table above. Duty cycle is 50/505% with a maximum frequency of 100 MHz. The 24M clock is fixed at 24 MHz. REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz. Note: BCLK buffers cannot be supplied with 5 volts (Pins 14 and 20) if CPU and fixed frequencies (Pins 1, 8 and 26) are being supplied with 3 volts. 2 ICS9159-12 Absolute Maximum Ratings Supply Voltage .......................................................................................................... 7.0 V Logic Inputs ....................................................................... GND 0.5 V to VDD +0.5 V Ambient Operating Temperature ............................................................. 0C to +70C Storage Temperature ........................................................................... 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 3.7 V DC Characteristics PARAMETER Input Low Voltage Input High V oltage Input Low Current Input High Current Output Low Current Output High Current Output Low Current Output High Current Output Low Voltage Output High V oltage Output Low Voltage Output High V oltage Supply Current SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH ICC VIN=0V VIN=VDD VOL=0.8V; for PCLKS & BCLKS VOL=2.0V; for PCLKS & BCLKS VOL=0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL=15mA; for PCLKS & BCLKS IOH=-30mA; for PCLKS & BCLKS IOL=12.5mA; for fixed CLKs IOH=-20mA; for fixed CLKs @66.66 MHz; all outputs unloaded TEST CONDITIONS MIN 0.7VDD -5.0 30.0 25.0 2.4 2.4 TYP 10.5 47.0 -66.0 38.0 -47.0 0.3 2.8 0.3 2.8 55 MAX 0.2VDD 28.0 5.0 -42.0 -30.0 0.4 0.4 110 UNITS V V A A mA mA mA mA V V V V mA 3 ICS9159-12 Electrical Characteristics at 3.3V VDD = 3.0 3.7 V AC Characteristics PARAMETER Rise Time 0.8 to 2.0V Fall Time 2.0 to 0.8V Rise Time 20% to 80% Fall Time 80% to 20% Duty Cycle [CPU] Duty Cycle, [REF(0:1)] Jitter, One Sigma Jitter, Absolute Jitter, One Sigma Jitter, Absolute Input Frequency Clock Skew Window Clock Skew Window Clock Skew Window SYMBOL Tr Tf Tr Tf Dt Dt Tj1s Tjab Tj1s Tjab Fi Tsk Tsk Tsk BH to BH; Load=20pF; @1.4V BP to BP; Load=20pF; @1.4V BH to BP; Load=20pF; @1.4V 20pF load 20pF load 20pF load 20pF load 20pF load 20pF load CPU Clock; Load=20pF, FOUT>25 MHz CPU Clock; Load=20pF, FOUT>25 MHz Fixed CLK; Load=20pF; Comp. to the period Fixed CLK; Load=20pF; Comp. to the period TEST CONDITIONS MIN 45 40 -250 TYP 1.5 0.9 2 1.8 50 50 1 2 14.318 50 50 100 MAX 3 2 4.5 4.25 55 60 150 250 3 5 250 250 500 UNITS ns ns ns ns % % ps ps % % MHz ps ps ps 4 ICS9159-12 SYMBOL MIN. A A1 A2 B C D E e H L N COMMON DIMENSIONS NOM. 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4 MAX. 0.078 0.008 0.070 0.015 0.008 0.212 0.311 0.037 8 0.068 0.002 0.066 0.010 0.005 0.205 0.301 0.022 0 VARIATIONS MIN. 14 16 20 24 28 30 34 36 44 48 56 0.239 0.239 0.278 0.318 0.397 0.397 0.701 0.602 0.701 0.620 0.720 D NOM. 0.244 0.244 0.284 0.323 0.402 0.402 0.706 0.607 0.706 0.625 0.725 MAX. 0.249 0.249 0.289 0.328 0.407 0.407 0.711 0.612 0.711 0.630 0.730 Ordering Information ICS9159F-12 Example: SSOP Package ICS XXXX F-PPP Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS=Standard Device ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 5 |
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